Verplex to Support Accellera Formal Property Language
Open Standard will Enable New Generation of Electronics Verification Tools, Libraries, Methodologies United Around One Language
MILPITAS, Calif.--(BUSINESS WIRE)--April 29, 2002--
Verplex(TM) Systems Inc., the electronic design automation (EDA)
formal verification market and technology leader, today added its
support for the formal property language selected by the Accellera
Formal Verification Technical Committee.
The language is the industry's first standard for formal
properties and was chosen after careful deliberation by members of the
Technical Committee, representing a wide variety of EDA companies and
their customers.
"Our goal is to add support for Accellera's formal language to our
support of its Open Verification Library (OVL) in a future release of
our BlackTie(TM) functional checker," notes Dr. Andy Lin, Verplex's
vice president of engineering. "Designers find OVL ideal for capturing
register transfer level implementation properties, while formal
languages offer system architects the desired flexibility for
capturing block-level interface constraints. The combination of the
two creates a powerful convergence in verification methodologies."
The creation of the language was an electronics industry
collaboration aimed at enabling a new generation of verification
tools, libraries and methodologies united around the single language.
Currently, multiple EDA vendors offer verification tools with
proprietary and incompatible formal languages, meaning that properties
must rewritten, and new languages learned, for different tools.
Widespread adoption of the Accellera language would mean a leap in
productivity for EDA vendors and customers alike. Vendors can focus
their resources to develop tools for a single language, and customers
can focus on using a common standard for developing property libraries
that can be reused with tools from multiple vendors.
"The Accellera Formal Verification Technical Committee defined an
open, transparent and fair process for selection of the new
industry-standard formal property language," remarks Harry Foster,
chairman of the Technical Committee and chief architect at Verplex.
"The language offers an opportunity to enable a huge leap in
productivity in electronics design and verification. It is critical
that the electronics industry now rally around the language, and
develop and demand tools based on it."
Mike O'Reilly, vice president of marketing for Cadence's Systems
and Functional Verification division, commented as well. "Cadence is
pleased to see that Verplex is fully participating in support of the
Accellera standardization efforts, which will enable cooperation among
EDA vendors in order to better solve the verification challenges that
our customers face."
About Verplex
Verplex Systems Inc. is an electronic design automation (EDA)
company focused on delivering the highest-speed, highest-capacity and
easiest-to-use formal verification products for complex system-on-chip
(SOC) design. Founded in 1997, it is privately held and funded by
leading venture capital firms. Corporate headquarters is located at
300 Montague Expressway, Suite 100, Milpitas, Calif. 95035. Telephone:
(408) 586-0300. Facsimile: (408) 586-0230. Email: info@verplex.com.
Online information is found at its web site: http://www.verplex.com.
Verplex, BlackTie, Conformal and Transformal are trademarks of
Verplex Systems Inc. All other companies and products referenced
herein are trademarks or registered trademarks of their respective
holders.
Contact:
Public Relations for Verplex
Nanette Collins
(617) 437-1822
nanette@nvc.com
